1. Field of the Invention
The invention relates generally to a semiconductor device and, more particularly, to a back-gate structure to control threshold voltage for a tri-gate field effect transistor.
2. Description of the Related Art
Tri-gate field effect transistors (Tri-gate FETs) on silicon-on-insulator wafers provide the advantages of fin-type field effect transistors (FinFETs) without requiring a relatively tall thin ‘fin’. As long as the height of the fin is comparable to the thickness of the fin and as long as the fin is fully depleted, the three-dimensional field effects of a tri-gate FET will give improved short-channel characteristics over a tall fin of the same thickness. Generally, the voltage threshold (Vt) of a tri-gate FET is set by work function selection and tuning or by adding donor or acceptor dopants. Consequently, the voltage threshold can not be controlled dynamically, nor can the voltage threshold be biased independently from FET to FET on the same chip. In addition, due to the statistical variation in the number of dopant atoms, unwanted voltage threshold variations can occur between FETs on the same chip. The invention described below addresses these issues by providing a back-gate structure for a tri-gate FET. The back-gate structure of the invention allows the threshold voltage for a tri-gate FET to be adjusted dynamically, for example, the threshold voltage may be increased when the transistor is not active and/or decreased when the transistor is active. Additionally, the back-gate structure of the invention allows for post fabrication adjustment of the voltage threshold for a tri-gate FET in order to improve control of chip leakage.